State of the art microelectronic systems commonly employ multichip modules. A multichip module includes an array of integrated circuit chips which require signal interconnections between the chips. Multichip modules having only electrical interconnections between chips have only limited performance and are not suitable for many next-generation highly parallel computational systems, for example. Since such computational systems require high density interconnection networks containing many relatively long distance interconnections, the minimization of the area, power and time delay of the chip-to-chip and module-to-module interconnections are critical.
Next-generation processor arrays will likely include hundreds of chips containing up to 512, or more, individual Processing Elements (PE's) per chip. Since efficient interconnection networks for many algorithms require at least one long distance connection per processing node, a multichip module capable of providing such a large number of interconnections per chip is desired. For a multichip module containing 64 chips, for example, over 32,000 high speed chip-to-chip interconnections would be required. In addition, module-to-module interconnections may be desired for increased processor array size, clock signal distribution, or communication with a controller or a shared memory. Accordingly, in such highly connected systems, the module-to-module and long distance chip-to-chip connections are responsible for the majority of the power dissipation, time delay and surface area consumed. Stated simply, the interconnections present a bottleneck to higher speeds of operation.
Fully electrically interconnected multichip modules are known in the art as disclosed in U.S. Pat. No. 4,774,630 to Reisman et al. A plurality of chips are mounted on a substrate in an inverted position so that the electrical connection pads are exposed on the upper surface of the chip. A passive "translator chip" is positioned over the electrical connection pads of the integrated circuit chip. The translator chip also covers a portion of the substrate surrounding the chip so that interconnections between the chip and the substrate are established. Unfortunately, the densities achievable with electrical interconnections alone are limited, since all chip-to-chip connections must be implemented with a small number (2-4) of planar layers. In addition, electrical interconnections are limited for signal fanout.
Optical interconnections have been developed with the potential to increase communication speed, and reduce the volume, crosstalk and power dissipation of electrical interconnections. Guided-wave optical interconnections are described in an article entitled "Optical Interconnects for High Speed Computing," by Haugen et al. and appearing in Optical Engineering, Vol. 25, pp. 1076-1085, 1986. U.S. Pat. No. 4,762,382 to Husain et al. also discloses optical channel waveguides formed on a silicon chip carrier to interconnect Gallium Arsenide (GaAs) chips. Silicon chips are also included on the chip carrier.
Although guided-wave optical interconnections have the advantages of low cost and low fabrication and packaging complexity, they have the disadvantages of inherent lower communication speed, less flexibility and less interconnection density capacity than holographic interconnections. The reduced interconnection capacity stems from the planar nature of guided-wave interconnections. Although in some cases two waveguides can cross at 90 degree angles with little crosstalk, it is difficult to achieve similar results with waveguides crossing at other angles. Since waveguides are formed by embedding a high index of refraction core material within a lower index cladding material, the optical signals in low loss waveguides travel at a relatively slower speed than free space propagation of the optical signals.
Holographic interconnections do not suffer from some of the limitations of the guided-wave optical interconnections. An article entitled "Interconnect Density Capabilities of Computer Generated Holograms for Optical Interconnection of Very Large Scale Integrated Circuits," by coinventor Feldman et al. which appeared in APPLIED OPTICS, Vol. 28, No. 15, pp. 3134-3137, Aug. 1, 1989, discloses free space optical interconnections between chips of a multichip module to increase interconnection densities. The chips may be arranged so that optical transmitters and detectors are on a common circuit plane, different circuit planes, or a mixture of both. Computer generated holograms are used to form the required optical interconnections. An article entitled "A Comparison Between Optical and Electrical Interconnects Based on Power and Speed Consideration", Applied Optics, Vol. 27, pp. 1742-1751, May 1, 1988, by coinventor Feldman et al. also discloses optical connections using one or more holograms.
Despite improvements in achieving higher interconnection densities, first with guided-wave optical interconnections, and later with free-space holographic interconnections, there still exists a need for higher densities and higher speeds of operation, such as required for highly parallel computationally intensive applications. In addition, as integrated circuit chip densities increase, there is an additional requirement that a multichip module having optical interconnections include facilities to readily remove excess heat from the chips.